Multi-gate transistors use a three-dimensional channel, which can be easily scaled. The multi-gate transistor can improve its current control capability even though its gate length is not increased. In addition, the multi-gate transistor can effectively suppress a short channel effect (SCE) of the voltage of a channel region being influenced by drain voltage.
As one of the scaling technologies for increasing the density of a semiconductor device, there has been proposed a multi-gate transistor in which a fin-shaped silicon body is formed on a substrate and a gate is formed on the surface of the silicon body.